A prior-art semiconductor memory device is usually provided with input circuits, and one of the input circuits is sometimes shared by an input signal and a programming signal or voltage Vpp and provided in association with a multi-purpose input terminal. The input circuit comprises an input signal circuit operative to propagate the input signal only, and a programming signal input circuit formed by a single transistor, thereby distributing the different signals to respective output terminals.
FIG. 1 is a diagram showing the circuit arrangement of an typical example of the prior-art input circuit incorporated in the semiconductor memory device. As shown in FIG. 1 of the drawings, the input circuit is associated with a multi-purpose input terminal 1 shared by the input signal IN and the programming signal or voltage Vpp and comprises an input signal circuit 2 coupled at the input node thereof to the multi-purpose input terminal 1 and at the output node thereof to an output terminal 4, and a programming signal input circuit 3 having an n-channel type MOS field effect transistor. The n-channel type MOS field effect transistor has the drain node coupled to the multi-purpose input terminal 1, the source node coupled to an output terminal 5 and a gate electrode to which a write-in data bit Di is supplied.
The behavior of the input circuit is described as follows.
When a memory cell array is ready for a read-out mode of operation, the multi-purpose input terminal 1 serves as a signal input terminal. Namely, the input signal circuit 2 receives the input signal supplied to the multi-purpose input terminal 1, and the output signal thereof is transferred to the output terminal 4. Since the write-in data bit Di remains in a low level at all times, the n-channel type MOS field effect transistor is turned off, thereby electrically isolating the output terminal 5 from the multi-purpose input terminal 1.
When the memory cell array is shifted to a write-in mode of operation, the multi-purpose input terminal 1 serves as a programming signal input terminal, so that the programming signal or voltage Vpp is supplied to the multi-purpose input terminal 1. The write-in data bit Di has been already shifted to a high level for writing the data bit of logic "1" level in one of the memory cell array specified by an address signal, and, accordingly, the n-channel type MOS field effect transistor 3 has been turned on. Then, the programming signal or voltage Vpp is transferred from the multi-purpose input terminal 1 to the output terminal 5. On the other hand, if no data bit of the logic "1" level is written into the memory cell array, the n-channel type MOS field effect transistor remains off due to write-in data bit Di of the low level, and, for this reason, the programming signal or voltage Vpp is not transferred from the multi-purpose input terminal 1 to the output terminal 5.
When the semiconductor memory device carries out the read-out mode of operation and the low level is supplied to the gate electrode of the n-channel type MOS field effect transistor at all times, the n-channel type MOS field effect transistor of the prior-art input circuit is liable to turn on due to an undershoot produced in the input signal IN applied to the multi-purpose input terminal 1. The n-channel type MOS field effect transistor is also liable to turn on under an application of noise swinging its voltage level into the negative voltage level. The n-channel type MOS field effect transistor is directly coupled at the drain node thereof to the multi-purpose input terminal 1 and at the source node thereof to the output terminal 5, so that the output terminal 5 is electrically coupled to the multi-purpose input terminal 1. The output terminal 5 is usually coupled to a sense amplifier circuit which is activated to quickly decide the logic level of the read-out data bit in the read-out mode of operation. The electrical connection between the multi-purpose input terminal 1 and the output terminal 5 results in reduction in voltage level at the output terminal 5, which has an undesirable influence on the read-out operation. Thus, a problem is encountered in the prior-art input circuit in the undesirable establishment of the electrical connection between the multi-purpose input terminal 1 and the output terminal 5.